Posts Tagged ‘Xilinx’

Get Ready to Bop It! With FPGA

Tuesday, April 26th, 2016


Hello FPGA enthusiasts! Today we have a close enough version of the popular Bop It! Game. For those unfamiliar with what a Bop It! Game is, I will tell you that it is practically a quick reflex based game that has a set of voice commands that give you instructions to perform tasks with the console.

As the game progresses, it gets faster paced and this is the challenge for any FPGA enthusiast.

There are basically 4 main points in this project:

  1. Figuring out the right functionalities and the right modules to use for them. Integrating them with your FPGA and coding it.
  2. Figuring the clock cycles needed for each module and ensuring that the separate clocks don’t clash with the main module of the program.
  3. LED displays instead of voice prompts are a stroke of genius from the author, but integrating this too can be a bit of work.
  4. External button compatibility with FPGA is the final and most crucial challenge, but where there is a will, there is a way!

The codes have been implemented in .vhd (VHDL) formats for easy compatibility with the hardware and the author has provided the different modules. This way the code can be better understood as it is broken into parts.

If you plan on implementing your own functionalities in the console you will have to key in your own codes and this can be a welcome challenge.

So embrace the opportunity to learn FPGA in a new light, and don’t forget to Bop It!

By omrinissan2013

How To Implement The Old Oberon System On A Modern FPGA

Thursday, February 11th, 2016


In today´s article we bring you an experiment carried out by Niklaus Wirth, a master of the Computer Science World. But this article goes beyond itself. It is much more than that because it is the introduction chapter for a thorough guide on how to implement the Oberon system, developed in the late 80´s on a modern FPGA.

The Oberon system was first created as a programming language to help academics teach system programming on a more simplified way. Later, in 1990 the Oberon Operating System was born. However, both the language and the operating system targeted a today-disappeared processor. Thus the main challenge was finding a modern processor that met the requirements. There was none, so let´s forget about this re-born Oberon thing…No! Mr. Wirth decided to take advantage of modern FPGA´s and build his own processor. This allowed him to also design both the hardware and the software. The chosen one, a Xilinx FPGA, made it possible to keep the design similar to the original one.


Flying high with Zynq

Tuesday, December 22nd, 2015

Open source enthusiast? Drone enthusiast as well? FPGA fan? Rejoice! The first Unmanned Air Vehicule combining all those technologies has recently been announced. It’s powered by a Xilinx Zynq processor running ArduPilot, and its source code is planned to be released. The team behind the project used a DJI F550 airframe and plans to test on more hardware. One of team founders says that using the FPGA part of the Zynq allows an easier real time processing, especially computationally intensive tasks. Before we see a video of the flight, we’re happy to learn that the Zynq board runs on Linux!


SparkFun Lunch and Learn: FPGAs for Makers, with Steve Grace

Thursday, September 18th, 2014

Steve Grace, a Xilinx Engineer, gives a nice presentation at SparkFun on FPGA’s. While this presentation is not geared for beginners it does an amazing job of introducing all of the tools and techniques available with FPGA’s once you get to the intermediate level. Steve also does a very nice job of showing how your HDL code maps to the physical elements on the FPGA and how you can dig in and take a look. If you are into FPGA’s it is definitely an educational video to watch. Thank you Steve and SparkFun!

Tune in this Friday, December 13th, at 1PM Mountain Standard Time, for a special LIVE Lunch and Learn from SparkFun Electronics! Field Programmable Gate Arrays (FPGAs) are extremely powerful parts with a steep learning curve. This presentation by FPGA engineer Steve Grace will go over what an FPGA is from both from the application and silicon perspectives, and introduce you to programming and development on Open Source Hardware. Steve will demonstrate code running on a Papilio Pro ( and Zedboard (, talk about how code maps to the hardware, and provide a high-level overview of in-chip debugging. One hour.

Welcome to the online home of The Zynq Book

Wednesday, September 3rd, 2014

Image of the Zynq BookCurious about the Xilinx ZYNQ processor – an FPGA core coupled with two ARM hard processors? Take a look at this free eBook released by Xilinx to learn more!

The Zynq Book is the first book about Zynq to be written in the English language. It has been produced by a team of authors from the University of Strathclyde, Glasgow, UK, with the support of Xilinx. We wanted to create an accessible, readable book that would benefit people just starting out with Zynq, and engineers already working with Zynq. We hope that it will prove a handy reference that remains on your desktop! You can find out more about the book’s contents on the About page.

Fun with PCI Express – Xilinx Wizard

Wednesday, September 25th, 2013

Xilinx provides a free PCI Express core “EndPoint Block Plus” and free Wizard to Configure it  with their free version of Xilinx-ISE WebPack.

So Open Xilinx Core Generator and select End Point Plus

Core Generator

Presently core is inactive, we need to  make it active first , On Menu Select File -> New Project to create project and select a FPGA  (if we are using Dragon-E so we select Virtex-5 otherwise whatever FPGA you are using select the same)

Xilinx core Generator


From Generation tab you can select language, either you want to develop your project in Verilog or VHDL etc.

Now the “EndPoint Block Plus” core becomes active and you can double-click on it to start the wizard.

On the first page, name your component. Here we chose “my_endpoint_blk_plus”. The rest is ok for Dragon-E, so click  Next >

Xilinx Core Gen

Now we can modify the Vendor/Device IDs

xilinx core gen

And we can also define or update address spaces

By Clicking  Next > will get some least bothered Menu items, so we can click on “Generate” to generate the core and its documentation.

After clicking Generate we will get the bit file , Now we can program our FPGA to Generate real PCI Express Traffic.

Clever Exploitation Of Vivado HLS To Make A FIR Filter And More

Tuesday, September 3rd, 2013

By way of Colin O’Flynn over at NewAE, we’ve got a wonderful video showing how to basically exploit the Xilinx HLS (High-Level Synthesis) in Vivado to make your own FIR filter in only about 25 minutes! I could attempt to write a synopsis of what is covered in the video, but as they say – a video is worth 10,000 words. It is a bit long, but if you’ve got the patience for it you might walk away with a couple of new tricks up your sleeve!

Vivado – it’s Xilinx’s new design tool system. Part of this is the ‘High Level Synthesis’ option – something you can also get it seems for ~$2k. I’m using these design tools in the “wrong” way, in that I’m generating HDL & then synthesizing it with the normal ISE chain. Some of the parts I’m using aren’t officially supported in Vivado it seems. Plus I’m currently more used to the ISE design flow, so don’t want to throw everything away.

After you watch the video, don’t forget to click on over to Colin’s site at NewAE to check out the full scoop.

(via NewAE)