Greetings FPGA lovers! Today’s project explores the possibility of using FPGA in combination with other processors to recreate the amazing Nintendo Chiptunes or Soundtracks that an entire generation of gamers are used to. The project uses a combination of FPGA with Verilog and the 6502 processor along with a Nesdev APU for audio generation.
The Hardware required for the project consists of the NIOS II FPGA, 6502 processor, Nesdev APU, SD card reader and a few other components needed to create the three primary blocks which are the timer block, length counter block and an envelope unit. These 3 blocks use a network of Mixers and PIOs besides the 5 channels available on the APU.
Out of the 5 channels available on the APU, only 4 channels have been used by the developers since the fifth channel (Delta Modulation Channel) is a time consuming endeavour. However the project does successfully emulate perfect chiptunes with the hardware. A detailed explanation of the Hardware used can be found here.
The coding used for this project is a combination of Verilog and C since FPGA and the 6502 are used. The Verilog Coding is used to extract Nintendo Sound Format files (.nsf) from the SD card reader onto the FPGA. The NSF files can be loaded on to the FPGA through the 6502 processor which has been coded in the C language using standard functions. NSF files can be stored on the SD card using a computer.
The NIOS II FPGA acts as an NSF player in this particular project. It can be used to control playback, stop tracks or forward and rewind to the next or previous track.
Using just 4 channels in the APU the developers have done an amazing job and an example of the fruits of their labour (and an inspiration!) can be seen here.