September 27th, 2016
Hello FPGA lovers! Engineering traditional synth machines using development platforms like Arduino and FPGAs is becoming quite the trend now. Today’s post however takes a twist from the traditional synth machines where sounds are produced by either flicking switches or pressing buttons. The synth machine under discussion is a photosensitive synth machine which uses LDRs interfaced with FPGA in place of button switches and this gives an almost touch screen like feel to the device.
The Hardware required is a FPGA board (adaption may be required), 16 LDRs, 16 high value resistors, a speaker, adequate jumpers and 2 breadboards. The entire project has only 2 sets of hardware implementation off the FPGA board. A speaker is directly wired to the FPGA board besides 16 LDRs which function as the photosensitive keyboard. These LDRs work as a 16 bit Keyboard that inputs signals to the FPGA board to convert to sound signals. The connection diagrams and screen shots are given here.
The coding used for the project has been done in VHDL and the author has given the codes in different modules. The note decoder module on Step 2 is one of the most crucial modules in the whole code as it assigns a particular frequency for the 16 bit value from the LDR keyboard. The sound generator module on Step 4 is the next crucial module as it sends the respective frequency (pitch) values to the speaker interfaced with the FPGA.
Through this link you will find the ucf files for the project. This can be modified according to your convenience in case you would like to add more functionality like sustain buttons and other effects.
September 20th, 2016
Hello FPGA enthusiasts! Today’s project takes you back to school where you learned the binary system. The author has designed a decimal to binary conversion game using FPGA. It is time to see if you did pay attention in class! The game uses a random number generator which generates any number between 0 and 255. Using the 8 switches on the FPGA, the player needs to guess the binary value right, following which the LEDs glow green. If you do go wrong, the LED matrix glows red showing you guessed incorrectly.
The FPGA board used for this project is the Nexys2 (you may need to adapt yours). It has an LED display, 8 switches and 8 LEDs which are perfectly suited for this project. Besides this some PMOD connectors, an 8×8 LED matrix, resistors, wires, daisy chain wires and 2 breadboards are the other hardware required. Steps 3, 4 and 5 of the project deals with understanding and connecting the hardware used for the project. Since the FPGA has a set of switches and a display, the extra hardware required is less for this project.
The programming language used by the author is VHDL. The program to run on the FPGA is available in step 9 as a zip file. The code has been broken down into modules for ease of understanding. Assigning the pins has been explained in detail in step 10, and the process of creating the bit file to run on the FPGA has been explained in step 11.
September 15th, 2016
Hello Papilio fans today we got an awesome project to share with you! Our forum member jlcollado has managed to migrate the Grant Searle’s brillant work called MULTICOMP to the Papilio DUO, the final result is a very usable and complete Z80 soft-core based machine, running the venerable Digital Research CP/M 2.2 OS.
I’ve built the Z80 CP/M variant, complete with VGA & Keyboard terminal, Serial port, SD-Card and external SRAM. The steps I followed to accomplish this:
1. Adapted the pinouts, ports and some signals of all the modules (Main Interconect, Z80, VGA, Serial, Keyboard, SD-Card) from the original design to fully use the Computing Shield peripherals and the DUO’s SRAM (using and updated Computing Shield UCF file).
2. Converted the original 6 bit color VGA to 12 bit color interface.
3. Converted the internal BIOS ROM and Character Font ROMs, to use Xilinx’s Core Generator’s Block Memory instead of the original Altera Altsyncram IP.
4. Converted the internal double port Display & Attribute RAMs also to use the Core Generator’s Block Memory instead of the original Altera Altsyncram IP.
5. In my first attempt I adapter the CPU and Baudrate clock generators, to use the Papilio’s 32 MHz OSC instead of the original 50 MHz, but I ran into timing problems converting the many clock -dependant constants in the design. So I decided to generate a new 50 MHz clock using the DCM & PLL Wizard.
For an in depth look at this great work please visit the project showcase page here, the full project files are also available on the same page.
Feel free to express your thoughts about the project in the comment section or in the original showcase page.
September 13th, 2016
The Zybo Board is one of the most powerful tools in FPGA and this is because it is FPGA combined with an ARM processor that widens the spectrum of possibilities with FPGA. Today’s post is yet another dive into Zybo’s possibilities and in this project a visualization of audio signals or music will be accomplished. The author has been very detailed about this project and has explained every aspect of it in 18 steps.
The Hardware needed for carrying out this project are the Zybo Zynq 7000 FPGA board, a neo pixel LED matrix, a 5V 10 A power supply, a female DC power adapter, 3 pin male to male header, a 1mF capacitor, an audio splitter and some jumper wires. The connection diagram is provided by the author in step 17.
The code basically uses the principle of FFTs to detect frequency components in the audio file. Depending upon the magnitude of frequencies received, the LED display has been programmed to light up. 16 steps starting from opening Vivado to run the code to generating a bit file for the FPGA has been provided by the author. You can download a zip file which contains all modules relevant to the project. The author has used a combination of C, custom Verilog and HDL to code the project. This gives an ease in defining GPIO ports and makes the circuit a lot simpler.
Another interesting aspect is that the FPGA has been so coded that with the help of switches, your LED matrix can either act as a spectrogram or as a visualizer seen in media players.
Let me challenge you to achieve similar results adapting your own FPGA!
September 8th, 2016
Hey there FPGA lovers! The human eye is far from being perfect, and this imperfection helps us in coming up with a lot of ideas and products (take the television for example!). Today’s post exploits the Human eye’s persistence of vision to build a globe of persistence using FPGA. These globes can be used to build circular LED displays using just 1 column of LEDs which make them highly cost effective and fun to build with FPGA.
The trick when it comes to the globe of persistence is to balance the RPM of the globe and the timing of the LEDs switching colour. The author has shared details regarding the hardware needed for the project in the introduction. An FPGA board (you may need to adapt yours for this project), a neopixel 12 LED strip, a 12 wire slip ring, a photo interrupter and a photo interrupter breakout board, a 12V DC motor, a micro SD card and a cross compiler for ARM processors.
The project also needs an interfacing board for the FPGA and globe which has been explained in step 2. Building the globe’s mechanical structure with the DC motor has been explained in detail in step 5, and soldering the wires in the right way has been shared by the author too.
The author has gone to great lengths to explain how to execute the project. Step 1 gives complete details about generating an FSBL file and a PDF in case you have doubts. The coding for the project has been done in Linux. But even if you are unfamiliar with Linux, the author has explained Linux for FPGA in detail in steps 3 and 4. The code has been broken down to modules, and there are clear instructions available on how to program the FPGA. Step 7 is the final step that explains how to get your globe working, and also gives details regarding building custom applications using the globe of persistence and FPGA.
September 6th, 2016
Hello FPGA innovators! Remember the arcade obstacle avoidance game where blocks of pixels fall on you and you steer clear of them moving left or right? Today’s project attempts to re engineer the same game using a VGA and FPGA. Here, a pseudo random code is used to generate obstacles that fall down and buttons on the FPGA are used to move the cursor so that none of the obstacles hit it.
The only hardware required to execute this project is an FPGA board (you might need to adapt yours if different from the author’s), a computer monitor and connection cables. This is because the FPGA board has inbuilt push buttons that can be used to move the cursor of the game, and also has the necessary DACs and VGA interfaces required to run the game.
The coding done by the author is in VHDL and everything starting from a functional flowchart to running the bit file for FPGA has been described from steps 1 to 9. Since the buttons on the FPGA has a bouncing issue, a separate debouncer code needs to be run which is available on step 2. Details regarding the VGA, coding for random obstacles and checking for collisions and updating the game are given from steps 3 to 7.
Though the authors put in 50+ hours of effort and made a great attempt, the game still could be done in a lot more simpler ways. The main code is available in the introduction to spare other followers from putting in more additional effort, but starting from choosing a different FPGA board to running through basics of other games implemented using VGA and FPGA can end up delivering something better with a lot less effort.
Give it a try and have fun!
September 1st, 2016
Greetings FPGA innovators! Stepper motors can be an integral part of projects that have a dimension of mobility to them. Be it rovers, robots, drones or claw machines, controlling stepper motors with joysticks is an integral part and FPGAs accomplish speed control easily. Today’s post is about using a FPGA and a joystick to control stepper motors.
The Hardware required for the project is a FPGA board, 2 PmodSTEP drivers, 1 PmodJSTK, 2 Stepper motors, a USB A to B micro cable and 2 12 pin PMOD cables. Since the author is only focused on the control of the stepper motors, the hardware for this project is limited. However it can be expanded based upon the scale of your endeavour.
The code structure is given by the author in step 2. The author has configured the PmodJSTK interface to receive data and not send data to the LEDs on the board. The working principle is pretty simple, where the decoder works out the signals from the Joystick and sends it to the drivers in the form of electrical signals that make the motors turn left, right, stay still or maintain course. The FPGA acts as a simple interconnect between the drivers. The code has been given in a zip file by the author in step 3.
The coding language used is VHDL and the code is divided into modules. Step 4 has been dedicated to code generation and creation of the executable bit file that can be used on the FPGA. Step 5 illustrates the connections for the project.