1. Adapted the pinouts, ports and some signals of all the modules (Main Interconect, Z80, VGA, Serial, Keyboard, SD-Card) from the original design to fully use the Computing Shield peripherals and the DUO’s SRAM (using and updated Computing Shield UCF file).
2. Converted the original 6 bit color VGA to 12 bit color interface.
3. Converted the internal BIOS ROM and Character Font ROMs, to use Xilinx’s Core Generator’s Block Memory instead of the original Altera Altsyncram IP.
4. Converted the internal double port Display & Attribute RAMs also to use the Core Generator’s Block Memory instead of the original Altera Altsyncram IP.
5. In my first attempt I adapter the CPU and Baudrate clock generators, to use the Papilio’s 32 MHz OSC instead of the original 50 MHz, but I ran into timing problems converting the many clock -dependant constants in the design. So I decided to generate a new 50 MHz clock using the DCM & PLL Wizard.