ZX Spectrum ULA Chip Implementation On OBLS

Above: OpenBench Logic Sniffer running the ZX Spectrum ULA chip clone.

As a follow-up to Friday’s article on the ZX Spectrum clone running on the Pipistrello, I thought it would be good to share a little more with you on the implementation of the Sinclair ULA chip. The chip was originally included in the ZX Spectrum microcomputer in 1982, and has since seen various reincarnations including this one. This particular implementation is done in Verilog and is FPGA ready. Here are the features supported:

  • CPLD (XC95144/288XL) version, with shared data bus, designed for the Harlequin clone.
  • FPGA (separate input and data buses, mostly synchronous, but I cannot aassure that) version, intented for soft SoC.
    • To test the FPGA version, several clones have been built around this ULA core. See directory branches/xilinx. These clones are ready to be used in the Spartan 3 Starter Board, both 200K and 1000K gate versions.
  • All timings according to Chris Smith’s specs. Yet to be tested against a real Z80 for timing accuracy (tv80 core seems not to have exact timings, but this could be my fault, not tv80′s)
  • Digital IRGB output, PAL timings. Same signals as found in the 128K heatsink RGB DIN connector, that is, bright component separated from main components.
  • 8 bit digital RGB output for ULA+ mode. Output signal indicate whether ULA is in normal or plus mode.
  • EAR, MIC and SPK pins
  • FPGA version adds the 8-pin row connector for keyboard matrix. See xilinx/ directory for design examples.
  • Timex Hicolor mode supported in the FPGA version of the core.
  • ULA+ implemented in the FPGA version of the core.

Head over to the ULA chip for ZX Spectrum page at Opencores to see the complete specs, more photos of this running on various platforms (including on the OpenBench Logic Sniffer), videos of the chip’s timing tests, videos of testing the Timex hicolor mode, and more.

(via Opencores)

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