How to Create a Visual Audio Spectrum with a FPGA in 5 Steps

August 30th, 2016

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Hello FPGA lovers! Today’s post is an interesting one which helps us visualize the audio spectrum with the help of your FPGA and an LED strip. Using a VGA cable, the spectrum can be visualised in a computer monitor as well. The microphone on the FPGA used (you may need to adapt this to your own board) captures the surrounding sounds and uses the FPGA to convert it into a perceivable visual output. The author has explained the principle of working in step 2. The input audio signal is stored in 2 block RAMs. The 1st RAM consists of the time domain representation which is used for display in the VGA. The 2nd RAM consists of the Frequency domain representation using FFT which is displayed both in the VGA and the LED strip.

The Hardware required for this project is a FPGA board, USB A to B micro cable, VGA cable, 30 LED Strip, VGA display (PC monitor) and 3 male to male jumper wires. The author has used the PC monitor as the VGA display for this project. However you can use a dedicated LCD screen or any other VGA display if you choose to. The hardware connections are explained in step 3.

The code is available as a zip file in step 4. The author has dedicated steps 4 and 5 towards installing and generating the program for the board. The language used is VHDL and the code has been broken down into modules. The zip file consists of the source files, a readme file explaining the code, a .tcl file to automatically build the project and the .bit and .bin files for programming the FPGA.

 

By Mirceadabacan

Save on Your Electricity Bill with Your FPGA

August 25th, 2016

https://youtu.be/Pi0lp_kIV58

Greetings FPGA innovators! Ever had the problem of forgetting to switch off the room lights on your way out? Do you have frequent guests who are not as mindful as you when it comes to power saving? In today’s project we see how to build a simple gadget with the FPGA to switch off your room lights once there is no one in. Not only will The FPGA trip light save power and work intelligently, but it will also help you cut power costs.

The Hardware needed for the project are a FPGA board (adaptation to your own device might be required), 2 off IR transceiver pairs, 4 off 1000 ohm resistors, 2 off 33 ohm resistors and 2 off 100 ohm resistors besides 2 breadboards and jumper wires. The author has shared details regarding the circuit setup, the FPGA board and the Breadboard connections in step 4. A housing model for the circuit has been shown in step 5 which will help the circuit to be used in a more compact and practical way.

The FPGA has been coded with the VHDL language. The black box diagram for implementing in the FPGA and its descriptions has been given in detail in step 2. The code has been divided into modules and has been given for ready availability in step 3.

The basic operation of the gadget is such that one transceiver pair counts the number of people entering the room, and the other counts the number of people leaving the room. The FPGA acts as a simple comparator and when both the counts are equal, the room lights are turned off.

 

By nyssabackes

Remotely Control your TV with Your FPGA

August 23rd, 2016

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Hello FPGA enthusiasts! The FPGA is truly a tool that can stretch the horizon of possibility and in today’s project we will find out how an FPGA can be used as an universal remote control. Ever had the problem of falling asleep while watching TV? Not anymore! The Universal Timed remote with FPGA is a timed remote which can be used to switch off any TV set once the timer ticks down!

The Hardware needed for this project are a FPGA Board, a breadboard, a 300 ohm resistor, male to male connecting wires and an IR LED and Sensor pair besides a TV set to test the device on. The circuit diagram has been given by the author in step 2.

The code has been written using VHDL and the VHDL setup for the FPGA is given in step 3. The code has been subdivided into modules and the whole file has also been attached in step 3 as a zip file. The main modules are the IR control and the Timer, which work in tandem to switch off the TV once the timer counts down.

Future enhancements and possible improvements have also been shared by the author. The timer can be set between 1 hour and 99 hours though it has been designed only to work for your own TV set. But a little bit of tweaking can make this a universal remote too!

 

By JoeD67

Very few know how Powerful this FPGA combination can be – Here is how to Control it

August 8th, 2016

https://youtu.be/zdlylcu8hQM

Greetings inhabitants of the FPGA world! Today’s post is about a project that can be a huge part of a number of other different projects that use FPGA as their core. Be it a claw machine or a drone or a navigator robot, interfacing Joysticks with FPGA will be a fundamental part of many of your future work. This article will help you control any device on a two dimensional platform with the code for movement in the XY plane. Moving in 3D (flight in the case of drones) can be easily achieved by using two joysticks in place of one.

The Author has wrapped up her project in a set of 5 steps to keep things short and sweet. The hardware needed for this project is simply a FPGA board, a system with Xilinx Vivado installed, Digilent PmodJSTK and a USB A to B micro cable. A general idea regarding the project is given in Step 2. The Joystick uses the SPI interface to receive and transmit data from and to the FPGA board.

The code for this project has been readily supplied in step 3 as a zip file. The contents can be sorted into a number of modules which have been coded in Vivado 2015.4. So using a different version of the software will mean you need to copy paste the codes into a new project file in your system.

The code can then be converted to bit stream to programme the board. You can also programme 2 joysticks (for Drones or RC Cars) since only the top bank of the PMOD Header in the FPGA board (you may need to adapt this to your own board) has been used for 1 joystick.

 

By Commanderfranz

The Daredevil Cam is Closer to Those with this Info and a FPGA

August 4th, 2016

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Hello FPGA hobbyists! Ever wondered what it would be like to see sound? The author thveryat very same curiosity for close to 10 years, and kept a constant vigilance for ideas to build something that would help him materialize his dreams. The Daredevil camera, built using a bunch of MEMS microphones and a FPGA actually lets you see sound.
The author started the project wielding inspiration from the Duga RADAR. However, the scale of the project becomes huge and something beyond what hobbyists can afford. The author then tried a more practical but tedious and time consuming design approach which involved using an array of microphones. Each microphone in the array picks the sound relative to its position and displays it on screen, which will always be different from the next microphone because of the difference in position.
While the logic behind this is sound, implementing an array of microphones, each having a Pre-amp stage and then an ADC stage before feeding inputs to the FPGA is not practical. The cost and time put into the project becomes huge, and even then error margins can be significantly high.
This is the reason why the author used a set of MEMS microphones. MEMS microphones have an inbuilt Pre-amp and ADC stage, and thus the project collapses in complexity. All that is needed is an array of MEMS microphones and an FPGA board to implement the project. FPGAs are FFT friendly and this has a huge part in the project.
The author has shared the PCB design layout here. Besides this a number of fail safes such as spare patterns for a Flash chip, SOIC and DIP. He also used micro SD cards for each array to store the data and send it for processing to get an output of close to 30 frames per second. The FPGA, a great tool for pipelining is used to get his output.
The author then tried out the theory in an 8×8 array and arrived at the conclusions that the device is pretty sensitive as it even picks up sound way reflections from surfaces. But since anechoic chambers are impossible to build at home, he went on to build a 16×16 array.
While the results can be seen in this page, the author is yet to perfect his design. There are persistent issues with micro SD card since its storage algorithm conveniently cuts off data to compress data, which is essential for the FPGA to build a 30 Frame/sec output.
To be heard…or seen.

 

By Artem Litvinovich

How to Make a Cleaner Planet with Your FPGA

August 2nd, 2016

Greetings FPGA fans! Today’s post takes power generation and conservation to another level! We all know that Solar Panels are an excellent source of non-conventional power. But if the panel is not facing the sun the power generation is never optimum. The sun changes its position continuously and a static solar panel can only generate optimum power for a short window of time when it directly faces the sun. But what if the solar panel too changed its position with respect to the sun? Then we would have a case where the panel generates optimum power for more than 8 hours which is a lot more compared to just the 1-2 hours it does when it is static!

Today’s project aims at making a dynamic solar panel with FPGA. This Dynamic Solar Panel changes its position according to the Sun’s position by making use of a comparator that compares voltage values periodically and rotates the panel. The hardware required for this project are 2 Bidirectional Parallax servo motors, a 9V DC Solar Panel, a FPGA, a Breadboard, A 3D Printed frame and 3 100 Ohm resistors.

The Project basically involves the use of an FSM designed by the author. The design steps have been explained in detail from steps 2 – 8. Any FPGA with sufficient inputs and outputs can be used for this project but the code shared by the author has been programmed for the Basys 3. So unless you’re feeling really adventurous, it would be best to follow what the author has done!

The program has been done in VHDL (.vhd) and is available here. It has been arranged into different modules and each module corresponds to one of the design steps from 2 – 8. The program is pretty easy to follow and improvising it to suit another FPGA board should be easy if you know VHDL.

The wiring has been shared in step 10. The author has used a 3D printed frame whose schematic has been shared in step 11. However if you plan on building your own frame from wood or cardboard, you can refer the sketches.

Let’ build a cleaner planet having fun!

By nickthequik

Build your own Mandelbrot Fractal Generator with FPGA

July 14th, 2016

Greetings FPGA lovers! Today’s post takes you into yet another interdisciplinary project that links pure mathematics, FPGA and VHDL to build something beautiful! The Mandelbrot set is a series of complex numbers that tend to infinity when operated upon by a special operator. These numbers when grouped together create a beautiful image sequence which might appear to be chaotic initially. But simplifying the set, we soon find that Mandelbrot’s numbers are nothing but fractals and this concept can be explored and understood visually with FPGA and VHDL.

Today’s project is an FPGA based Fractal explorer that has been built out of the Papilo Duo kit which includes Xilinx Spartan 6 LX9 FPGA, an ATmega 32U4 microcontroller and a 512 MB Static RAM. Some other hardware needed is a basic 7” LCD screen, a Joystick, a few buttons and a rotary encoder.

The colour map shown in the project is navigated by using the joystick to move around, rotary knob to chose colour scheme and the buttons to zoom in and out. These controls are connected to the ATmega 32U4 microcontroller which is interfaced with the FPGA through an SPI interface.

The LCD has been tweaked to display 800 x 600 and the FPGA has also been correspondingly set to process 800 x 600 pixel fractals using the inbuilt DSP 48s. The project is inspired by the Mandelbrot Fractal Generator by Hamster.

Though the code for this project is still unavailable at the moment, you can refer Hamster’s project to get the basic dataflow and code in the C language. Once you do have the logic at hand, the project can easily be converted to the FPGA/VHDL combination instead of the Computer/C combination used by Hamster.

The project is an excellent way to continue learning coding through VHDL and get used to the Papilo Duo Kit.

 

By Larry McGovern

Recreating Nintendo Chiptunes with FPGA and the 6502 processor

July 12th, 2016

https://www.youtube.com/watch?v=rf_p3-8fTo0

Greetings FPGA lovers! Today’s project explores the possibility of using FPGA in combination with other processors to recreate the amazing Nintendo Chiptunes or Soundtracks that an entire generation of gamers are used to. The project uses a combination of FPGA with Verilog and the 6502 processor along with a Nesdev APU for audio generation.

The Hardware required for the project consists of the NIOS II FPGA, 6502 processor, Nesdev APU, SD card reader and a few other components needed to create the three primary blocks which are the timer block, length counter block and an envelope unit. These 3 blocks use a network of Mixers and PIOs besides the 5 channels available on the APU.

Out of the 5 channels available on the APU, only 4 channels have been used by the developers since the fifth channel (Delta Modulation Channel) is a time consuming endeavour. However the project does successfully emulate perfect chiptunes with the hardware. A detailed explanation of the Hardware used can be found here.

The coding used for this project is a combination of Verilog and C since FPGA and the 6502 are used. The Verilog Coding is used to extract Nintendo Sound Format files (.nsf) from the SD card reader onto the FPGA. The NSF files can be loaded on to the FPGA through the 6502 processor which has been coded in the C language using standard functions. NSF files can be stored on the SD card using a computer.

The NIOS II FPGA acts as an NSF player in this particular project.  It can be used to control playback, stop tracks or forward and rewind to the next or previous track.

Using just 4 channels in the APU the developers have done an amazing job and an example of the fruits of their labour (and an inspiration!) can be seen here.

 

By A. Heil and S. Zhao